Lim HeeYeon

ssmp7203@gmail.com

https://heyhy823.github.io/

 

Education

2015/03 – 2019/02             B.S., Applied Statistics

                                           Konkuk University, Seoul (GPA: 4.16 / 4.5)

 

2015/03 – 2019/02             B.S., Computer Science Engineering

                                           Konkuk University, Seoul (GPA: 3.97 / 4.5)

 

Research Interests

- Optimization Algorithms & Data-Driven System Development 

-  Design of optimization frameworks for semiconductor validation tests.

-  Devlopment of automated data analysis pipelines to enhance efficiency of hardware evaluation.

-  Semiconductor Domain-Specific Data Analytics

-  Analysis of semiconductor performance metrics using advanced statistical methods, including regression analysis and two-sample t-tests.

- Application of machine learning and statistical insights to optimize semiconductor manufacturing processes.

- Statistical Modeling & Reliability Analysis

- Application of statistical methods to identify key factors affecting semiconductor reliability.

-  Development of performance prediction model to minimize variation and defect rate.

 

Professional Experience

2021/02 – Present            Flash I/O Characteristic Enhancement & E-Fuse Optimization Frameworks Development

-  Designed E-Fuse optimization system to enhance Flash I/O characteristics, including signal-integrity, power-integrity, and speed.

-  Designed an automated measurement pipeline system for test equipment.

-  Designed domain-specific optimization algorithm to imporve product performance and efficiency.

-  Built data pipeline systems for efficient evaluation data management and in-depth analysis.

 

2023/06 – 2025/01            DRAM I/O Characteristics Optimization Algorithm Design Considering Board Variations

- Designed a Test Mode Register Set(TMRS^[1]) optimization algorithm using circuit simulation methodologies to improve DRAM I/O characteristics(timing and voltage).

-  Designed an automated measurement system for test equipment to enhance reliability and efficiency.

-  Designed an optimization system for BIOS(DDR5 Booting Firmware) configurations to streamline evaluation, significantly reduce evalutaion turn-around time.

 

2022/10 – 2025/01            DRAM Production Validation Algorithm Design and Analysis System Development for Intel

-  Designed validation algorithms through reverse engineering.

-  Designed a prediction model for validation defect rates and developed a system for upper-bound/lower-bound scenario analysis to estimate performance limits.

-  Developed a pre-processing system for package performance analysis and designed data pipelines to enhance efficiency.

 

2020/02 – 2021/02           Flash Core E-Fuse Optimization System Development

-  Designed a genetic Algorithm to optimize Flash E-Fuse, ensuring compliance with performance, variation, and reliability specifications.

-  Developend a Real-time raw data pre-processing system.

-  Statistical insights and semiconductor design domain knowledge utilization to resolve product issues.

-  Developed a data processing pipeline.

 

 

Patent

2023.03             [Method for quantifying contribution of trimming parameter and generating post-silicon validation tests], No. US18/506435, A2, 2023-11-10, US

 

Skill

2024.11            OPIC IH (English Speaking Test)

 

2020.02            SW(Software) Certification: Samsung SW Professional grade

 

Award & Honors

2024.06           DRAM Development Division - Q2 Regular Award(Collaboration/Synergy Category)

-  Developed a statistics-based sequential logic tool for optimizing Rank Margin Test (RMT^[2]) characteristics

2022.08           Memory 3.0 Excellence Award

-  Automated Server/Client BIOS TMRS^[1] settings for DDR5 RMT^[2] measurements.

2022.06           Q2 Design Platform Division Quarterly Award

-  Collaborated on product performance and variation by developing specialized applications.

 

Programming skills

C/C++, Git, Python, Pytorch